The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a dynamic threshold (DT) complementary metal oxide semiconductor (CMOS) field effect transistor (FET) device and method for forming same.
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced. High device density also requires low-power operation.
The push for ever increasing device densities is particularly strong in CMOS technologies, such as in the design and fabrication of field effect transistors. FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.). Unfortunately, increased device density in CMOS FETs can result in degradation of performance and/or reliability.
One type of FET that has been proposed to facilitate increased device density is a dynamic threshold CMOS field effect transistor. Dynamic thresholding is achieved by electrically connecting the gate to the body, so that the body voltage moves with the gate voltage, lowering the threshold voltage when a signal is present. Dynamic thresholding provides faster response time and lower power consumption for the FET. Threshold voltage (Vt) is high in the off-state, limiting power leakage, and low in the on-state, limiting power requirements. CMOS generally uses less power than ordinary MOS. Dynamic threshold CMOS uses less power than standard CMOS.
Unfortunately, several difficulties arise in the design and fabrication of DT CMOS FETs. First, the connection between the gate and the body contact in prior art DT CMOS FETs is inevitably a long, high-resistance path. That high resistance degrades the response time of the circuit. Second, the body-to-source/drain capacitance in existing DT CMOS FETs limits the speed of the circuit. Neither result is desirable in CMOS applications. Unfortunately, these two practical limitations counterbalance the response time increase otherwise available from dynamic threshold CMOS.
Thus, there is a need for improved device structures and methods of fabrications of DT CMOS devices that provide dynamic threshold operation without paying the performance cost of high resistance gate-body contact and high body-to-source/drain capacitance. Only then can the full potential of DT CMOS be realized.
In a first aspect the invention comprises a method for forming a transistor, the method comprising the steps of a) providing a semiconductor substrate; b) patterning the semiconductor substrate to provide a first body edge; c) providing a gate structure adjacent the first body edge; d) patterning the semiconductor substrate to provide a second body edge, the first and second body edges of the semiconductor substrate defining a transistor body; e) providing a body contact structure adjacent the second body edge aligned to the gate structure; and f) providing an electrically connective bridge between the gate structure and the body contact structure over the transistor body.
In a second aspect, the invention comprises A transistor comprising: a) a transistor body formed on a substrate, the transistor body having a first vertical edge and a second vertical edge; b) a gate structure adjacent the transistor body first vertical edge; c) a body contact structure adjacent the transistor body second vertical edge and aligned with the gate; d) a bridge over the body, the gate, and the body contact, electrically connecting the gate and the body contact; and e) source and drain regions in the body on opposite ends of the body.
Accordingly, the present invention provides a fin-based dynamic threshold (DT) complimentary metal oxide semiconductor (CMOS) field effect transistor (FET) and methods for forming same that results in improved device performance and density. The method and apparatus applies to both nFETs and pFETs.
The foregoing and other advantages and features of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.